In an information processing apparatus such as a server or a personal computer, a two-line type serial bus similar to an I2C (registered trademark) bus is sometimes used. The two-line type serial bus is used, for example, for coupling of a device of a comparatively low speed such as a peripheral device.
When a unit having a device is hot-line connected into a two-line type serial bus, a phenomenon sometimes appears that current flows from a bus line to the terminal side of the unit but within a very short time period (for example, several nano-seconds) through a capacitor component (stray capacitance) of a signal line in the inside of the unit.
FIG. 14 is a view illustrating an influence on a bus line by a stray capacitance in the inside of a unit when the unit is hot-line connected into the bus line. As depicted in FIG. 14, the unit has a stray capacitance that depends upon an internal circuit. While the bus line is maintained at a given voltage level by a pull-up resistor, if the unit is hot-line connected into the bus line, then charge current i to the stray capacitance of the unit flows from the bus line. At this time, since the voltage level of the bus line drops instantaneously by outflow of the current i from the bus line to the unit, there is the possibility that some other device coupled with the two-line type serial bus may malfunction.
For example, a method described is known in order to prevent malfunction of some other device by addition of a unit to a two-line type serial bus.
FIGS. 15 and 16 are views depicting examples of a configuration of information processing apparatus 100 and 100′ individually including an I2C bus.
First, the example depicted in FIG. 15 is described. As depicted in FIG. 15, the information processing apparatus 100 includes an Micro Processing Unit (MPU) 120, an I2C bus controller 130, an IO_PORT input 110, an IO_PORT output 111 and bus switches 140a and 140b. Further, the information processing apparatus 100 includes pull-up resistors 150 and 160, a connector 170, a power supplying unit 180 and I2C devices 210-2 and 210-3. Further, an additional unit 200 includes an I2C device 210-1, a power supply unit 220 and a connector 230.
The MPU 120 is a processor that performs monitoring and control of the I2C devices 210-1 to 210-3 (where the I2C devices 210-1 to 210-3 are not distinguished from each other, each of them is hereinafter referred to simply as I2C device 210). The MPU 120 is coupled with the IO_PORT input 110, IO_PORT output 111 and I2C bus controller 130 through a local bus 310.
The IO_PORT input 110 detects that the additional unit 200 is connected to the information processing apparatus 100. Here, the IO_PORT input 110 is coupled with the connector 170 through amounting signal line 340 maintained at a given voltage level by the pull-up resistor 160. Further, a mounting signal line 340 that is coupled to the ground (GND) is coupled with the connector 230 of the additional unit 200. If the connector 170 is coupled with the connector 230, then the mounting signal line 340 is coupled to the GND through the mounting signal line 420. Therefore, the IO_PORT input 110 detects, when the voltage of the mounting signal line 340 drops, that the additional unit 200 is connected to the information processing apparatus 100.
The I2C bus controller 130 is coupled with the I2C device 210 through a serial bus (I2C bus) 320 maintained at a given voltage level by the pull-up resistor 150 and performs communication control of a data signal and a clock signal with the I2C device 210.
The BUS-SWs (bus switches) 140a and 140b are switches interposed between a data signal line (SDA) 320a and a clock signal line (SCL) 320b included in the serial bus 320 and the connector 170, respectively. The bus switches 140a and 140b switch coupling between the corresponding signal lines and the I2C device 210-1 of the additional unit 200 coupled through the connectors 170 and 230, respectively. It is to be noted that both of the bus switches 140a and 140b are placed into a disable state if the additional unit 200 is coupled with the connector 170 and release the coupling between the serial bus 320 and the I2C device 210-1, namely, place the coupling into a cut state.
The IO_PORT output 111 performs switching of coupling by the bus switches 140a and 140b through control lines 330a and 330b under the control of the MPU 120.
It is to be noted that, if the connector 230 of the additional unit 200 is connected to the connector 170, then the power supplying unit 180 supplies power to the power supply unit 220.
In the information processing apparatus 100 configured in such a manner as described above, if the additional unit 200 is mounted, then the IO_PORT input 110 detects connection of the additional unit 200 through variation of a mounting signal of the mounting signal line 340 from High to Low (refer to an arrow mark (1) of FIG. 15).
If it is recognized by referring to the IO_PORT input 110 that the additional unit 200 is connected, then the MPU 120 causes the I2C bus controller 130 to temporarily stop operation for bus access of the serial bus 320 (refer to an arrow mark (2) of FIG. 15).
Further, within a time period within which the serial bus 320 stops, the MPU 120 controls the IO_PORT output 111 to switch the bus switches 140a and 140b to an enable state (refer to an arrowmark (3) of FIG. 15). Consequently, the bus switches 140a and 140b are closed and the SDA 320a and the SDA 410a of the additional unit 200 are rendered conducting, and the SCL 320b and the SCL 410b of the additional unit 200 are rendered conducting.
If the bus switches 140a and 140b are switched to an enable state, then the I2C bus controller 130 restarts operation for bus access to perform bus access to the I2C device 210-1 of the additional unit 200 (refer to an arrow mark (4) of FIG. 15).
By the operation described above, the MPU 120 temporarily stops the bus access of the serial bus 320 and couples the additional unit 200 to the serial bus 320. Consequently, an influence of noise (voltage drop) upon contact of the additional unit 200 with the bus line by a capacitor component (stray capacitance) of the signal line of the additional unit 200 can be suppressed. In particular, since the noise of voltage drop appearing when the additional unit 200 is coupled with the connector 170 is separated by the bus switches 140a and 140b in a disable state, an influence is not had on the serial bus 320.
Now, the example depicted in FIG. 16 is described. While, as depicted in FIG. 16, the information processing apparatus 100′ includes a configuration similar to that of the information processing apparatus 100 depicted in FIG. 15, the information processing apparatus 100′ is different from the information processing apparatus 100 in that an I2C bus multiplexer 112 is included in place of the IO_PORT output 111 and bus switches 140a and 140b. 
The I2C bus multiplexer 112 is an I2C device interposed between the serial bus 320 and the I2C device 210 and connector 170. It is to be noted that, as the I2C bus multiplexer 112, a PCA9542 fabricated by NXP Semiconductors or the like is available.
The I2C bus multiplexer 112 performs channel switching of the serial bus 320 between a channel 1 for the I2C devices 210-2 and 210-3 in the inside of the information processing apparatus 100′ and a channel 2 for the I2C device 210-1 of the additional unit 200. In particular, the I2C bus multiplexer 112 performs channel switching at a timing at which the bus is not in a busy state. It is to be noted that the I2C bus multiplexer 112 includes a register in the inside thereof, and, if a value indicating channel switching is written into the register through the I2C bus controller 130 by the MPU 120, then the I2C bus multiplexer 112 starts detection of a timing at which the bus is not in a busy state.
In the information processing apparatus 100′ configured in such a manner as described above, if the additional unit 200 is connected, then the IO_PORT input 110 detects the connection of the additional unit 200 similarly to the information processing apparatus 100 (refer to an arrow mark (1) of FIG. 16).
After the detection of the connection of the additional unit 200, the MPU 120 performs channel switching control for the internal register of the I2C bus multiplexer 112 through the serial bus 320 before accessing to the additional unit 200 (refer to an arrow mark (2′) of FIG. 16).
The I2C bus multiplexer 112 performs switching from the channel 1 to the channel 2 at a timing at which the bus is not in a busy state based on the value of the internal register (refer to an arrow mark (3′) of FIG. 16).
If the channel is switched by the I2C bus multiplexer 112, then the I2C bus controller 130 performs bus access to the I2C device 210-1 of the additional unit 200 (refer to an arrow mark (4) of FIG. 16).
By the operation described above, when the bus is not in a busy state, the I2C bus multiplexer 112 switches the channel to couple the additional unit 200 with the serial bus 320. Consequently, similarly as in the example depicted in FIG. 15, an influence of noise (voltage drop) upon contact of the additional unit 200 with the bus line by the capacitor component (stray capacitance) of the signal line of the additional unit 200 can be suppressed. In particular, since noise of voltage drop appearing when the additional unit 200 is coupled with the connector 170 is separated by the I2C bus multiplexer 112, an influence is not had on the serial bus 320.
It is to be noted that, as a related technology, an exchanging technique of a module during online operation of a system is available (for example, refer to Japanese Laid-open Patent Publication No. 9-44280). In the technology, a bus switch performs coupling/decoupling of a module at a timing at which malfunction does not occur even if noise appearing upon insertion/removal of the module is received by some other module coupled with the bus.
Here, an example depicted in FIG. 17 is available as a timing at which malfunction does not occur even if noise is received by some other module. FIG. 17 is a view illustrating a timing of coupling or decoupling of a module with or from a bus. For example, in a parallel bus, some other module receives data at a timing of a rising edge of a bus clock. In other words, even if noise is generated when an additional modules is coupled with a bus, if the noise has disappeared when data is received in synchronism with the bus clock, then some other module can receive data (data “B” of FIG. 17) without being influenced by the noise.
Further, as a different related technology, a technology is known that a coupling state between a bus and a unit is switched in response to a state of the bus or the unit by a switch interposed between the bus and the unit (for example, refer to Japanese Laid-open Patent Publication No. 2008-197752 and Japanese National Publication of International Patent Application No. 2004-528627).
Further, a technology is known that the potential level of a bus of a computer main body is controlled to set the potential level to a potential level equal to that of a bus at the expansion unit side so that bus coupling with an expansion unit is achieved when a bus cycle is in an execution state (for example, refer to Japanese Laid-open Patent Publication No. 9-237140).
In the information processing apparatus 100 depicted in FIG. 15, the MPU 120 stops operation of the I2C bus 320 under the control of software for the I2C bus controller 130. While it is originally desirable to place such a shared bus as the I2C bus 320 in a state in which the bus can always access a device, in the information processing apparatus 100, it is difficult to perform continuous access to the different device 210 when the additional unit 200 is coupled with the shared bus.
Further, in the information processing apparatus 100′ depicted in FIG. 16, the I2C bus 320 is branched and is complicated in bus configuration by the provision of the I2C bus multiplexer 112. In order to add an additional unit 200 to the complicated bus configuration, the MPU 120 performs channel switching control by software for the I2C bus multiplexer 112. Accordingly, the information processing apparatus 100′ has, in addition to the difficulty of performing the continuous access to the different device 210 when the additional unit 200 is coupled with the shared bus similar to that of the information processing apparatus 100, there is a possibility that delay of processing occurs in the channel switching control by the MPU 120.
Further, the technology described hereinabove with reference to FIG. 17 is applied to a parallel bus. Even if the technology is applied to an I2C (serial) bus, when noise appears on a clock signal upon coupling of an additional module, there is the possibility that some other module may fetch data in error.
It is to be noted that, in the technology described above that a coupling state between a bus and a unit is switched by a switch in response to the state of the bus or the unit, it is not taken into consideration that an influence of noise appearing when the unit is coupled is suppressed.
Further, since, in the technology that the potential level of a bus of a computer main body is controlled to set the potential level to a potential level equal to that of a bas at the expansion unit side, complicated control by software is performed, there is a possibility that delay of a coupling process of the expansion unit occurs.
As described above, in the technologies described above, a bus is subject to various influences upon coupling of a device.